Existing programmable logic devices (PLD's) have a predetermined fixed number of power and ground pins wherein the other pins of the device are typically used as a normal input/output (I/O) site. However, depending upon the application, more or less power and ground pins may be required. For example, suppose a first pin is utilized as an I/O site to output a high power signal. In this case, it may be desired to have a plurality of pins (more than the fixed number) that are positioned adjacent and nearby to the first pin to be power and ground pins thereby minimizing switching noise problems especially if there exists many simultaneously switching outputs. Moreover, as the density of PLD's increases, programmable pins are quite desirable to allow optimum allocation of input/output, power and ground pins for a given application.
Hence, there exists a need to provide a circuit for allowing a user to program pins of a programmable logic device to be either an I/O site, a power pin or a ground pin.